Issue 2 – Volume 1

VLSI Circuits and Systems Letter 


Volume 1, Issue 2, October 2015 

A Web-Enabled Letter which can be navigated either through use of the following headings or the tiles below.

Volume 1, Issue 2, October 2015

Editorial

Features

Opinions

Updates

  • Upcoming conferences and workshops
  • Call for papers and proposals
  • Funding Opportunities
  • Job Openings
  • Ph.D. Fellowships Available

Outreach and Community

Call for Contributions
For readers preferring an all-inclusive pdf copy please feel free to download the PDF Version!


 

Editorial – v1_2

Editorial

The VLSI Circuits and Systems Letter is affiliated with the Technical Committee on VLSI (TCVLSI) under the IEEE Computer Society. It aims to report recent advances in VLSI technology, education and opportunities and, consequently, grow the research and education activities in the area. The letter, published twice a year, covers the design methodologies for advanced VLSI circuit and systems, including digital circuits and systems, analog and radio-frequency circuits, as well as mixed-signal circuits and systems. The emphasis of TCVLSI falls on integrating the design, computer-aided design, fabrication, application, and business aspects of VLSI while encompassing both hardware and software.
TCVLSI sponsors a number of premium conferences and workshops, including, but not limited to, ASAP, ASYNC, ISVLSI, IWLS, SLIP, and ARITH. Emerging research topics and state-of-the-art advances on VLSI circuits and systems are reported at these events on a regular basis. Best paper awards are selected at these conferences to promote the high-quality research work each year. In addition to these research activities, TCVLSI also supports a variety of educational activities related to TCVLSI. Several student travel grants are sponsored by TCVLSI in the following meetings: ASAP 2015, ISVLSI 2015, IWLS 2015, and SLIP 2015. Funds are provided to compensate student travels to these meetings as well as attract more student participation. The organizing committees of these meetings undertake the task of selecting right candidates for these awards.
This issue of the VLSI Circuits and Systems Letter showcases the state-of-the-art developments covering several emerging areas: radiation-hardened circuit, design for manufacturability, hardware IP protection, mixed-signal design and internet of things (IoT). Professional articles are solicited from technical experts to provide an in-depth review of these areas. The articles can be found in the sections of “Features” and “Opinions”. In the section of “Updates”, upcoming conferences/workshops (including their call for papers), funding opportunities and job openings are summarized. Finally, a dedicated section of “Outreach and Community” discusses the approaches for outreach with several successful stories.
We would like to express our great appreciation to all Associate Editors (Mike Borowczak, Prasun Ghosal, Shiyan Hu, Helen Li, Anirban Sengupta and Yiyu Shi) for their dedicated effort and strong support in organizing this letter. The complete editorial board information is available at: http://www.tcvlsi.org/vlsi-circuits-and-systems-letter/editorial-board/. We are thankful to our web chair Mike Borowczak, for his professional service to make the letter publically available on the Internet. We wish to thank Saumya Bhadauria, Anirban Sengupta, Bei Yu, Elias Kougianos and Prasun Ghosal who have contributed their professional articles to this issue. We hope that you will have an enjoyable moment when reading the letter! The call for contributions for the next issue is available at the end of this issue and we encourage you to submit articles, news, etc. to an associate editor covering that scope.

Design for Manufacturability: From Ad Hoc Solution to Extreme Regular Design

Feature, Issue 2, News

Design for Manufacturability: From Ad Hoc Solution to Extreme Regular Design

Bei Yu
Department of Computer Science and Engineering,The Chinese University of Hong Kong, Hong Kong

1. Introduction and Motivation

In very large scale integrated (VLSI) circuit design, shrinking transistor feature size using advanced lithography techniques has been a holy grail for the whole semiconductor industry. However, the gap between the manufacturing capability and the design expectation becomes more and more critical for sub-28nm technology nodes. Under the constraint of 193nm wavelength lithography, advanced circuit designs are vulnerable to many reliability issues, such as open/shorts, performance degradation, or parametric yield loss. There are several lithography techniques to overcome these issues [1]. In emerging technology node and the near future, multiple patterning lithography (MPL) has become the most viable lithography technique. Generally speaking, MPL consists of two different manufacturing processes: litho-etch type and self-aligned patterning type. In the longer future (for the logic node beyond 14nm), there are several next generation lithography options, such as extreme ultra violet (EUV), electron beam lithography (EBL), directed self-assembly (DSA), and nanoimprint lithography (NIL).
Design for manufacturability (DFM), in conjunction with process integration challenges, are being actively research, to provide friendliness to these lithography techniques. For MPL, there are intensive investigations to solve layout decomposition, where the input layout is divided into several masks (e.g. [2–6]). Besides, some research work considers particular MPL constraints in early design stage, such as placement [7, 8] and routing [9–11]. For EUV, to migrate the mask blank defect, layout patterns are relocated to avoid the defect impact [12]. Also, related design constraints to avoid blank defect can be integrated into early physical design stage (e.g. [13]). For EBL, since its key limitation is the low throughput, many approaches have been developed to improve the system throughput [14–16]. For DSA, how to design and verify the guiding template patterns, which form DSA holes insides, have been investigated in [17] and [18], respectively.
However, so far most of the DFM research is merely providing ad hoc solutions. That is, one specific work is targeting at one particular lithography constraint, and one work is hard to be re-used by another one where a new lithography constraint is involved. Therefore, CAD vendors may have to prepare a bunch of technical supports to these emerging design challenges. Recently there is a trend that different lithography techniques may be combined to provide better printability (e.g., MPL+EBL [19] and MPL+DSA [20]). Due to such trend, in the near future, the situation may be even worse that more and more CAD tools and design supports are required.
Extreme regular design is a promising solution for DFM community to resolve the diverse design challenges [21, 22]. Fig. 1 gives an example of such extreme regular layout [23], where we can see that the layout can be decomposed into line patterns and cut patterns. The benefit of such regularity is twofold. On the one hand, although various resolution enhancement techniques (RET) are utilized, random geometrical configurations are still hard to implement due to lithography limitation. Extreme regular style is able to improve the manufacturability and achieve manageable post-layout processing complexity. As shown in Fig. 1, the regular layout is the ease of splitting into line patterns and cut patterns. This allows independent process optimization of the line patterns and cut patterns. On the other hand, extreme regular design is naturally friendly to different emerging lithography techniques. For example, the cut patterns can be easily manufactured using EBL, DSA, or MPL.

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Figure 1: Regular design can be decomposed into lines and cuts [23].

2. Current Research for extreme Regularity

a. Standard Cell Design Stage
Standard cell design is a critical stage for providing overall layout regularity. There have been some cell synthesis works for regular standard cells [24–27]. However, while the yield and performance benefits of regularized layouts may be well accepted, the biggest barrier to broader implementation of regularized layout styles is the perceived impact on layout density and intra-cell routability [28]. Recently, a Tungsten-based middle of line (MOL) structure is introduced to connect intra-cell transistors [29]. MOL structure is made up of two different local interconnection layers, CA and CB (sometimes called IM1 and IM2, respectively), where the CA layer is used as a connection layer for active fins and better landing for the contacts in active region, while the CB layer is mostly used for via landing and gate shortening [30].
Ye et al. [31] studied the problem of cell layout regularity optimization under MOL structure. Fig. 2 gives an example of the proposed cell optimization, where the input 2D cell in older technology node is shown in Fig. 2(a), while the optimized unidirectional cell is in Fig. 2(b). Due to the unidirectional shapes of MOL and Metal-1 layers, the patterns are SADP friendly. That is, the line-space array decomposition can be applied to SADP with trim masks, with tight control on overlay and wafer-print artifacts. A general integer linear programming (ILP) formulation is proposed to solve the unidirectional cell optimization under MOL structure. Besides, a set of hybrid techniques is presented to search for high quality cell optimization solution.
For regular layout design, several works have been done on the investigation of contact layer fabrication and contact layer optimization. Yi et al. [32] demonstrated the fabrication of regular standard cell contacts using DSA process. Besides, Du et al. [17] proposed a contact layer optimization method. By assigning cost function to different DSA templates based on their manufacturability, they optimized the DSA aware contact layer. Recently, Ou et al. [33] performed a comprehensive investigation on the DSA based end-cutting problem, where a mathematical formulation is proposed to search for minimum wire extensions and minimum conflicts for all test cases.

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Figure 2: Example of cell regularity optimization in [31]. (a) The input layout with ten tracks. (b) The optimized layout with nine tracks.
b. Detailed Routing Stage

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Figure 3: The 1D target patterns in (a) can be formed by a 1D nanoarray with (b) 2D irregular or (d) 1D regular line-end cut patterns. (c) The wafer images of 2D irregular cut patterns suffer from distortion and degrade the printability of line ends. (e) The wafer images of 1D regular cut patterns have better line-end printability [35].

Detailed routing aims at pin access and search for exact routes of each net. A typical detailed routing strategy performs pathfinding of the nets sequentially. [34, 35] proposed a comprehensive framework to explicitly address the regular routing under regular layout constraints. Fig. 3 illustrates an example of such regular detailed routing result. The wafer image quality of irregular 2D line-end cut patterns in Fig. 3(c) suffers from more severe pattern distortion than that of 1D cut patterns in Fig. 3(e) [35].

3. Further Work

There is a large amount of emerging design challenges, along with the regular design style. In the following three of them are listed.
• Firstly, due to limited local routing resources and dense I/O pins, pin access is still a serious problem for detailed routing. To overcome the local congestion problem, physical design tools should be aware of the congestion derived from the dense I/O pin cells. For instance, in placement stage local congestion mitigation can be applied to prevent placing hard-to-routed cells too close together [36]. More importantly, the standard cell library should be carefully designed to enhance the pin accessibility. That is, I/O pins need to be balanced distributed within a cell, as the alignment or the densely packing of pins make the cell more difficult to be accessed.
• Secondly, under regular design style, although the printability and yield is improved, one standard cell may suffer from area and timing penalty. How to optimize the cell layout while timing constraints are satisfied is a critical problem.
• Thirdly, a coherent physical design framework is imperative. Although there are some attempts on extreme regular routing (e.g. [34, 35]), how to handle the extreme regular design style across the placement and routing stage is still an open problem.

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